Integrated circuitry fabrication typically involves lithographic processing whereby a desired circuitry image is formed in an imaging layer. The image is transferred to underlying circuitry layers on a substrate by using the imaging layer as a mask during etching or other removal of underlying material exposed through the imaging layer. Further, in many instances it is desirable to form the same type of devices from a commonly deposited conductive layer to have different dimensions, including having different base widths of such devices.
Integrated circuitry fabricators are ever attempting to increase circuitry density and thereby reduce the size of individual conductive components. As device dimensions decrease, interest is increasing in using alternatives to lithographic definition of features, particularly in an effort to achieve device dimensions that are smaller than the available, yet ever decreasing minimum feature resolution using lithography.
Various vertical device structures are under investigations that make use of controlled deposition as a means of creating small features, with the base width dimension thereby being controlled largely by the deposition thickness of the layer. For example, it is possible to deposit conductive material over a vertical wall to a known desired thickness, and then remove it from horizontal surfaces by anisotropic reactive ion etching. This leaves a vertically extending conductive component having a base width essentially equal to the deposition thickness of the conductive layer. Such techniques have historically also been utilized to form insulative spacers over field effect transistor lines.
It would be desirable, although not required, to develop improved methods which enable both subresolution processing and fabrication of multiple width electronic device components using presently and yet-to-be-developed photolithographic and other masking processing.